1. Field
The disclosed invention relates to packaging of microchips and, more specifically, to packaging microchips using fan-out wafer or panel level packaging.
2. Related Art
There are two major advanced semiconductor packaging technologies considered as members of the fan-out packaging family. The two are Fan-Out Wafer Level Packaging (FOWLP), and Fan-Out Panel Level Packaging (FOPLP). For FOWLP, a saw is used to singulate dies from a processed wafer having multiple completed chips thereupon. The individual dies are then placed on a wafer-shaped substrate and overlaid to be embedded in a low cost material such as epoxy mold compound (EMC), polyimide, etc. (referred to collectively herein as molding compound). This forms a sacrificial wafer, generally referred to as reconstituted wafer, with spaces allocated between each die for additional I/O connection points. Redistribution Layers (RDL) are then formed to re-route I/O connections on the dies to the mold compound regions in the periphery. Since the reconstituted wafer is of similar size and shape as standard silicon wafer, the RDL processing can be done using standard semiconductor processing systems.
While molding compound is a cost-effective material for this application, it readily absorbs moisture when exposed to atmosphere. Outgassing from the molding compound during the redistribution formation can have detrimental effects on device contact resistance (known as RC or RVIA) so an effective degas process is essential. However, the molding compound material has low thermal budget of less than about 120° C. to prevent decomposition and excessive wafer warp. Consequently an effective degas requires low temperature and long process time, thereby significantly reducing system throughput on traditional single wafer-based degas systems.
Fan-Out Panel Level Packaging is somewhat similar to FOWLP, except that the chips are arranged on a large tray, generally rectangular, and the mold material is flown over the tray. Due to the size and shape of the panel, the RDL cannot be processed in standard semiconductor processing equipment, however depending on size, it may be processed using flat panel display equipment, generally referred to as Gen 2 or Gen 3.
A solution is needed that enable processing FOWLP and FOPLP for forming the redistribution layers while maintaining high throughput, providing effective outgassing at low thermal budget, and cleaning the contacts without causing any damage to the chips and especially avoiding electrostatic damage (ESD).